intel 8255A/82C55ADevice Description
intel 8255A/82C55A
Q1. What is the device?
Q2.
Are there any Application Notes, Tech Bits, or Errata?
Q3.
Why is the 8255A/82C55 needed?
Q4. What
peripheral devices can work with the 8255A/82C55A?
Q5.
How does it work?
Q6. How does the
8255A/82C55A actually accomplish the interface activity?
Q7.
How is the 8255A/82C55A used?
Q8. Can the
8255A/82C55A be programmed immediately after the system is
powered-up?
Q9. When can RESET be applied
to the device with respect to the application of Vcc?
Q10.
What is the state of the 8255A following power-up? Is there a
possibility of spurious outputs?
Q11.
How are the devices packaged?
Q12. What
is the parameter tRV found in the data sheet timing diagrams?
Q13.
Is a customer able to drop an 82C55A device into the NMOS 8255A
socket? Should a customer be concerned about the ability of the chip
to drive a Darlington pair?
Q14. What
are the two data sheet parameters IPHLO and IPHHO (Port Hold Low/High
Overdrive Current)?
Q15. How many
transistors are there in the 8255A and 82C55A?
Q16.
When the 8255A is programmed in Mode 0 as an output, can data be read
back without reprogramming the chip?
Q17.
What will happen if the Strobe line is tied low?
Q18.
What is the current drive capacity of the 8255A and 82C55A?
Q19.
By reprogramming one port, what is the effect on the remaining
ports?
Q20. When is data latched in Mode
1?
Q21. Why is the STB# setup time (tPS)
0ns and the hold time (tPH) 180ns?
Q22.
Can WR# precede CS#?
Q1. What is the device?
A1.
The 8255A/82C55A interfaces peripheral I/O devices to the
microcomputer system bus. It is programmable by the system software.
It has a 3-state bi-directional 8-bit buffer which interfaces the
8255A/82C55A to the system data bus.
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Q2. Are there any
Application Notes, Tech Bits, or Errata?
A2. Ap-15, 8255
Programmable Peripheral Interface Applications, shows software and
flow charts for modes. There are Tech-Bits for Reading from Output
Ports and a Port Hold Device Description found in Lotus Notes. ASMO
Apps also has a Tech-Bit on the World Wide Web concerning interfacing
two 8255A's together.
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Q3. Why is the 8255A/82C55
needed?
A3. It reduces the external logic normally needed to
interface peripheral devices. The 8255A/82C55A replaces a significant
percentage of the logic required to support a variety of byte
oriented input/output interfaces.
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Q4. What peripheral devices
can work with the 8255A/82C55A?
A4. Printers, keyboards,
displays, floppy disk controllers, CRT controllers, machine tools,
D-to-A and A-to-D converters, etc. Connections to these peripheral
devices are made via the 8255A/82C55A Port Pins.
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Q5. How does it
work?
A5. Every peripheral device in a microcomputer system
usually has a "service routine" associated with it. This
routine manages the software interface between the device and the
CPU. By examining the I/O devices interface characteristics for data
transfer and timing, and matching this information to the examples
and tables in the operational description, a control word can be
developed to initialize the 8255A/82C55A to exactly "fit"
the application. Data is transmitted or received by the device buffer
upon execution of input or output instructions by the CPU. Control
words and device status information are also transferred through the
data bus buffer.
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Q6. How does the
8255A/82C55A actually accomplish the interface activity?
A6.
1. The device has 24 I/O pins which may be individually programmed in
2 groups of 12 and used in 3 basic modes of operation. The modes can
be selected by the system software. The modes are:
MODE 0 - Basic Input/Output: Each group of 12 I/O pins may be programmed in sets of 4 to be input or output.
MODE 1 - Strobed Input/Output: Each group of 12 I/O pins may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals.
MODE 2 - Bi-Directional Bus: 8 lines are used for a bi- directional bus, and 5 lines (borrowing one from the other group of 12) are used for handshaking.
2. The RD#, WR#, A0 and A1 (Port Select 0 and Port Select 1) signals are input into the device. The Read/Write Control Logic issues control words to the device Group A and Group B Controls. The Group A and Group B Controls, in turn, issue commands to the associated ports. The Control Groups are defined as:
Control Group A: Port A and Port C upper
(C7-C4).
Control Group B: Port B and Port C lower (C3-C0).
3. The device contains three 8-bit ports (A, B, and C). These 3 ports receive control words from the Group A and Group B Controls. These 3 ports have special features:
PORT A: One 8-bit data output latch/buffer and one 8-bit data input latch.
PORT B: One 8-bit data input/output latch buffer and one 8-bit data input buffer.
PORT C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for the input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B.
Q7. How is the 8255A/82C55A
used?
A7. The specifications for the peripheral device are
examined to determine the control and data signals which must be
supported by the 8255A/82C55A. The 8255A/82C55A is then programmed to
provide the correct I/O and data paths.
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Q8. Can the 8255A/82C55A be
programmed immediately after the system is powered-up?
A8. Yes,
but it takes less software to do a device reset via the device reset
pin and then program the 8255A. The sequence should be:
1. System power.
2. Device reset (to put it
in a known state).
3. Program it as desired.
Q9. When can RESET be
applied to the device with respect to the application of Vcc?
A9.
RESET can be applied no earlier than 50ns after Vcc is
applied (8086 specification).
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Q10. What is the state of
the 8255A following power-up? Is there a possibility of spurious
outputs?
A10. The chip is in an unknown state following
power-up. The possibility of spurious output during power-up always
exists, however, there are no known instances of this. A reset should
be used following power-up. This clears the control registers and all
ports (A,B,C) are set to the input mode.
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Q11. How are the devices
packaged?
A11. The 8255A comes only in a P-dip package. The
82C55A comes in P-dip and plcc.
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Q12. What is the parameter
tRV found in the data sheet timing diagrams?
A12. The
parameter tRV is not found in the 82C55A or 8255A wave forms.
However, it is the time between reads and writes, as stated in the
8255A data sheet.
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Q13. Is a customer able to
drop an 82C55A device into the NMOS 8255A socket? Should a customer
be concerned about the ability of the chip to drive a Darlington
pair?
A13. All three ports of the 82C55A can source 2.5mA and
drive Darlington pairs. The user must limit the current the chip
sinks to the data sheet limits. The 82C55A still requires external
pull-ups. The internal pull-ups designed to terminate the unused port
pins in the 82C55A function if the pins are loaded with less than
20pF. Loads greater than 20pF will not have the logic level
guaranteed by the internal pull-ups. Refer to the tech bit covering
the port hold device description.
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Q14. What are the two data
sheet parameters IPHLO and IPHHO (Port Hold Low/High Overdrive
Current)?
A14. There is a 4-page tech-bit called Reading from
Output Ports and another called Port Hold Device Description. The
definition of the two parameters IPHHO and IPHLO is the current
necessary to overcome the port-hold devices. For example, if a
pull-up device sources 300uA when active, it will require an external
device to sink 350uA minimum to turn off that pull-up.
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Q15. How many transistors
are there in the 8255A and 82C55A?
A15. 8255A: 5800
transistors; 82C55A: 5200 transistors.
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Q16. When the 8255A is
programmed in Mode 0 as an output, can data be read back without
reprogramming the chip?
A16. Yes, but since each port has
slightly different circuitry, different values will be read.
1. The value read from Port A will represent the physical state of the output pins, i.e., if an output pin is shorted to ground, the value read from Port A would always be 00H, regardless of the value written.
2. The values read from Ports B and C are different. These values represent the state of the output latch, not the physical state of the pins as in Port A. If Ports B or C were shorted to ground, as in the above example, the last value written will be read regardless of the fact that the physical pins of Ports B or C are shorted to ground.
Q17. What will happen if
the Strobe line is tied low?
A17. STB# must not go low while
IBF is active. It may go low up to 300ns before IBF goes to active
status in the 8255A and 150ns before IBF goes to active status in the
82C55A. If STB# were to go low when IBF is active, the peripheral
will overwrite the previously written data which had not been read by
the CPU. When STB# is tied low while initializing the 8255A, the chip
will lock up and will not allow any data transfers to be made.
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Q18. What is the current
drive capacity of the 8255A and 82C55A?
A18. Any set of eight
output buffers from Ports B and C can source between 1mA and 1.5mA,
allowing the 8255A to drive Darlington type drivers and high voltage
displays which require this source. Port A does not have this
capacity since it sources only minimal current. All three ports in
the 82C55 can source 2.5mA.
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Q19. By reprogramming one
port, what is the effect on the remaining ports?
A19. Writing
a control word to reprogram one port affects the operation of the
other ports, even if that one port is reprogrammed to exactly the
same mode. This means the device cannot be reprogrammed "on the
fly". The effects on each port are different depending on the
mode.
1. Port A:
All Modes: Output data is
cleared, input data is not cleared.
2. Port B:
Mode 0: Output data is cleared,
input data is not cleared.
Mode 1 and 2: Both output and input
data are cleared.
3. Port C:
Mode 0:Output data is cleared,
input data is not cleared.
Mode 1 and 2: IBF and INTR are cleared
and OBF# is set. Outputs in Port C which are not used for
handshaking or interrupt signals are cleared. Inputs such as STB#,
ACK#, or "spare" inputs are not affected. The interrupts
for Ports A and B are disabled.
Q20. When is data latched
in Mode 1?
A20. Data is latched on the rising edge of the
8255A Mode 1 STB# handshaking signal. This question typically arises
when the designer is attempting to accommodate some external device
or logic which does not provide the RD#, STB#, and IBF signals within
the data sheet specifications. In general, if STB# does not go high
the data read from that port may or may not be valid. STB# should go
high prior to a RD# of the port data to guarantee that the data is
valid.
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Q21. Why is the STB# setup
time (tPS) 0ns and the hold time (tPH) 180ns?
A21. The
internal setup for latching data occurs on the falling (leading) edge
of STB# and during the STB# low time (similar to a WR# operation). In
most peripheral interface applications, the data setup time is not
predictable but the hold time is, thus the long hold time spec of the
8255A (180ns) versus the short setup time (0ns). Data should remain
stable during STB# low time, but the absolute requirement is stable
data at STB# rising (trailing) edge and the data must remain stable
during tPH.
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Q22. Can WR# precede
CS#?
A22. Yes. All relevant timings must also be reversed to
provide correct setup and hold timing. This signal reversal is not a
supported interface but several customers have used it with no
reported problems.
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Information © 1998 Intel
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Documen)