GameBoy Opcode Summary

The GameBoy has instructions & registers similiar to the 8080, 8085, & Z80 microprocessors. The internal 8-bit registers are A, B, C, D, E, F, H, & L. Theses registers may be used in pairs for 16-bit operations as AF, BC, DE, & HL. The two remaining 16-bit registers are the program counter (PC) and the stack pointer (SP).

The F register holds the cpu flags. The operation of these flags is identical to their Z80 relative. The lower four bits of this register always read zero even if written with a one.

Flag Register

The GameBoy CPU is based on a subset of the Z80 microprocessor. A summary of these commands is given below.

MnemonicSymbolic OperationCommentsCPU ClocksFlags - Z,N,H,C

8-Bit Loads

LD r,sr ss=r,n,(HL)r=4, n=8, (HL)=8
LD d,rd rd=r,(HL)r=4, (HL)=8
LD d,nd nr=8, (HL)=12
LD A,(ss)A (ss)ss=BC,DE,HL,nn[BC,DE,HL]=8, nn=16
LD (dd),A(dd) Add=BC,DE,HL,nn
LD A,(C)A ($FF00+C)-8
LD (C),A($FF00+C) A8
LDD A,(HL)A (HL), HL HL - 18
LDD (HL),A(HL) A, HL HL - 18
LDI A,(HL)A (HL), HL HL + 18
LDI (HL),A(HL) A, HL HL + 18
LDH (n),A($FF00+n) A12
LDH A,(n)A ($FF00+n)12

16-Bit Loads

LD dd,nndd nndd=BC,DE,HL,SP12----
LD (nn),SP(nn) SP -20
LD HL,(SP+e)HL (SP+e)1200**
PUSH ss (SP-1) ssh, (SP-2) ssl, SPSP-2 ss=BC,DE,HL,AF16----
POP dd ddl (SP), ddh (SP+1), SPSP+2 dd=BC,DE,HL,AF 12

8-Bit ALU

ADD A,sA A + s CY is the carry flag. s=r,n,(HL)r=4, n=8, (HL)=8*0**
ADC A,sA A + s + CY
SUB sA A - s *1**
SBC A,sA A - s - CY
AND sA A s*010
OR sA A s *000
XOR sA A s
CP sA - s*1**
INC ss s + 1 s=r,(HL)r=4, (HL)=12*0*-
DEC s s s - 1 *1*-

16-Bit Arithmetic

ADD HL,ssHL HL + ss ss=BC,DE,HL,SP8-0**
ADD SP,eSP SP + e 1600**
INC ssss ss + 1 8----
DEC ssss ss - 1 8


SWAP sSwap nibbles. s=r,(HL)r=8, (HL)=16*000
DAAConverts A into packed BCD.-4*-0*
CPLA /A4-11-
CCF CY /CY CY is the carry flag.4-00*
SCFCY 14-001
NOPNo operation.-4- ---
HALTHalt CPU until an interrupt occurs.4
DIDisable Interrupts.4
EIEnable Interrupts. 4

Rotates & Shifts

RLC ss=A,r,(HL)r=8, (HL)=16*00*
RL s
RR s
SLA ss=r,(HL)r=8, (HL)=16

Bit Opcodes

BIT b,sZ /sbZ is zero flag. s=r,(HL)r=8, (HL)=12*01-
SET b,ssb 1r=8, (HL)=16----
RES b,ssb 0


JP nnPC nn-16
JP cc,nnIf cc is true, PC nn, else continue.If cc is true, 16 else 12.
JR ePC PC + e 12
JR cc,e if cc is true, PC PC + e, else continue.If cc is true, 12 else 8.


CALL nn(SP-1) PCh, (SP-2) PCl, PC nn, SPSP-2 -24
CALL cc,nnIf condition cc is false continue, else same as CALL nn.If cc is true, 24 else 12.


RST f(SP-1) PCh, (SP-2) PCl, PCh 0, PCl f, SPSP-2 - 16


RETpcl (SP), pch (SP+1), SPSP+2 -16
RET ccIf cc is true, RET else continue.If cc is true, 20 else 8.
RETIReturn then enable interrupts.16


-Flag is not affected by this operation.
*Flag is affected according to result of operation.
bA bit number in any 8-bit register or memory location.
CCarry flag.
cc Flag condition code: C,NC,NZ,Z
dAny 8-bit destination register or memory location.
ddAny 16-bit destination register or memory location.
e8-bit signed 2's complement displacement.
f8 special call locations in page zero.
HHalf-carry flag.
NSubtraction flag.
NCNot carry flag
NZNot zero flag.
nAny 8-bit binary number.
nnAny 16-bit binary number.
rAny 8-bit register. (A,B,C,D,E,H, or L)
sAny 8-bit source register or memory location.
sbA bit in a specific 8-bit register or memory location.
ss Any 16-bit source register or memory location.
ZZero Flag.